This invention relates to memory modules, and more particularly to dynamic, timed termination circuits.
Personal computers (PCs) and other electronic systems often use memory modules such as dual-inline memory modules (DIMMs). Memory modules have memory chips such as dynamic-random-access memories (DRAMs) mounted on a small printed-circuit board (PCB) or other substrate. Contact pads along one edge of the substrate make electrical contact when the memory module is plugged into a socket such as on a PC motherboard.
As these electronic systems operate at higher and higher speeds, signals driven to the memory modules must also operate at higher frequencies. Faster high-current drivers can be used to more rapidly drive current to charge and discharge the capacitances on the inputs of DRAM chips on the memory modules. These DRAM-input capacitances can be significant, producing a large capacitive load on the inputs to the memory modules, especially when many DRAM chips are mounted on the same memory module.
As clock rates rise above 100 MHz, metal traces on circuit boards behave as transmission lines, exhibiting reflections, undershoot, overshoot, and ringing that distort signals. This can be true of memory modules operating at higher frequencies. Transmission-line techniques such as termination resistors may be added to signal lines on memory modules to suppress reflections and other transmission-line effects.
FIG. 1A shows a terminated signal trace on a typical memory module. Buffer 10 on a memory module substrate or on a motherboard drives near end 12 of a metal trace or line. DRAM chips 14 each have an input connected to the metal line between near end 12 and far end 16. DRAM chips 14 can be clocked or synchronous DRAM chips (SDRAM). The line between ends 12, 16 may be an address line, but could be other address or control lines generated by a memory controller on a PC motherboard.
Contact pads along an edge of the memory module make electrical contact with metal tabs inside the memory module socket. When buffer 10 is mounted on the memory module substrate, the contact pads connect to traces to inputs of buffers such as buffer 10. Other signals may connect directly to DRAM chips 14 without on-substrate buffering. Some DIMM modules may have fewer or more DRAM chips than the 9 shown in this example.
To suppress reflections along the line between ends 12, 16, resistor 18 is added to far end 16. Resistor 18 may connect to a middle voltage such as Vtt, which can be half of the Vcc power supply. Other systems may use some other voltage for Vtt, even power or ground.
FIG. 1B is a waveform showing termination currents. When the signal applied to DRAM chips 14 rises from ground to Vcc, the voltage at far end 16 rises, as shown in waveform 20. Current through resistor 18 reverses direction as the far-end voltage rises above Vtt, as shown in waveform 22.
Termination Itt current initially flows in a positive direction from Vtt, through resistor 18 to the grounded line at far end 16, but stops flowing when the voltage at far end 16 rises to Vtt. As the far-end voltage continues to rise above Vtt, current flows from far end 16, through resistor 18 to Vtt, which is now at a lower voltage. This is considered to be negative current, −Itt.
Termination current remains −Itt while far end 16 is high, even though no switching is occurring. When buffer 10 switches to driving near end 12 high-to-low, as far end 16 falls in voltage the termination current again switches direction. Once far end 16 is driven to ground, the maximum termination current, +Itt, flows through resistor 18.
Thus termination current is at maximum absolute values when switching stops. Current is continuously drawn through termination resistor 18 when address signals to DRAMs 14 are staying high or low. This can be a serious power drain from the termination voltage source, and a significant amount of heat can be generated by resistor 18 and other termination resistors that must be dissipated by a heat sink attached to the memory module.
The termination current is +/−Itt when far end 16 is high or low. This can be a substantial current. For example, resistor 18 may have a value of 50 ohms to match the trace impedance between ends 12, 16. Vtt may be set to 0.9 volt for a 1.8-volt Vcc supply. The current Itt is V/R or 0.9/50=18 mA. This is the current through one termination resistor for one signal line. A memory module may have many address and control lines, each having two far ends when lines are driven from the middle, requiring as many as 50 termination resistors. The total termination current on one memory module may approach 1 Amp. Some memory modules have large cumbersome heat sinks attached to dissipate the heat generated in part from such large termination currents.
Active termination circuits can be used in place of static termination resistors. See for example U.S. Pat. No. 6,686,763 by Yen, and assigned to Pericom Semiconductor Corp. This active termination circuit uses a transition detector to switch the active termination on and off. Transitions on the line being terminated are detected and used to turn on the active termination. While useful, the transition detector may be triggered by noise on the line, and may not be on for the very start of a transition.
What is desired is an active terminator for memory modules. A dynamic termination circuit that uses the synchronous nature of SDRAM chips is desired rather than a transition-detector-based active terminator.